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We are looking for an outstanding Senior Networking Software Architect to join the NIC/DPU Software and Firmware Architecture group. In this role, you will help define the next generation of our datacenter and AI networking platforms, with focus on DPU management, QoS, performance, telemetry, and software architecture across stacks. You will work closely with hardware designers, firmware/kernel driver teams, system engineers, validation, product management and customers. The role spans early architecture definition, pre-silicon design, bring-up, and production readiness for large-scale AI and cloud datacenter deployments.

What Youll Be Doing:

Own software and system architecture for next-generation DPU management, QoS, performance, telemetry, and observability features.

Define end-to-end control and management flows across DOCA, host drivers, embedded firmware, BMC, management controllers and external management systems.

Specify telemetry and observability requirements, including counters, logs, traces, events, health monitoring, debug data, and streaming telemetry.

Define management interfaces and APIs for configuration, provisioning, lifecycle operations, diagnostics, and field serviceability.

Write clear architecture specifications, interface definitions, flow diagrams, and design documents for software, firmware, and system teams.

Partner with R&D teams to translate high-level architecture into implementable designs and guide features through development, validation, silicon bring-up, and production.

Analyze system performance bottlenecks, interoperability issues, telemetry gaps, and customer-reported issues, then feed learnings into future architecture.

Collaborate with system and cluster architects to ensure NIC/DPU features fit end-to-end AI datacenter and cloud networking designs.

We are seeking a Senior System Management Architect to lead the management architecture for our advanced SmartNIC cards. You will be the resident expert for SmartNIC system management, ensuring that NIC ASICs, Baseboard Management Controllers (BMCs), MCUs, CPUs, and CPLDs operate in perfect unison. You will own the lifecycle management specifications for SmartNIC platforms-from factory provisioning and day-one deployment to complex orchestrated reset flows and secure recovery. If you are someone who enjoys looking at a high-level system diagram and then immediately diving into the I2C/I3C bus topologies and PLDM command structures required to make it work, this role is for you.

What you'll be doing:

System Architecture & Flow Definition: Define and document comprehensive production, provisioning, update, recovery and reset flows for SmartNIC cards. Crucially, you will ensure that these board-level architectural decisions perfectly align with and support overarching platform-level needs, orchestrating seamless coordination between the NIC ASIC, BMC, CPU, and peripheral components.

Security & Provisioning: Specify security provisioning flows including OTP fusing, secure boot enablement, attestation key injection, certificate chain management, RPMC key derivation, and PQC (Post-Quantum Cryptography) requirements. Define IPN-to-OPN transition and component locking procedures.

Protocol Implementation & Guidance: Specify the use of standard management protocols (MCTP, PLDM, SPDM, NC-SI) across internal board interfaces to achieve secure boot, firmware updates, and telemetry gathering.

Hardware/Software Intersect: Dive deep into device-level hardware and software behaviour. Define CPLD logic requirements, power-sequencing dependencies, and reset orchestration (e.g., handling PCIe PERST#, SBR, and forced resets) for multi-host and standalone SmartNIC environments.

Interface Management: Architect intra-board communication pathways using PCIe, I2C/I3C, USB, and SPI, ensuring robust out-of-band (OOB) and in-band management connectivity.

Cross-Functional Leadership: Collaborate tightly with Production teams, Hardware and Firmware Engineering, NIC FW/Driver teams, and QA to translate your architectural specifications into implementable, testable realities.

Technical Documentation: Author rigorous technical specifications, test plans, and architectural design documents to guide both development and factory production.

Our HW team in Israel is looking for an experienced System Engineer to join the Hardware Switch Group. The team leads the development of networking infrastructure for our next-generation data centers focusing on accelerated performance while enabling optimized end to end GPU connectivity.

What you'll be doing:
CPO (Co Package Optic) Switch System architecture and design from concept to mass production.
Define the HW requirement, HW arch, board partition and lead electro-optic-mech concept. In addition - design/review HW aspects such as schematics, component selection, layout, opto-mechanics, DFM/T.
Collaborate and integrate with all HW project fields: Board Design, Mechanics, Thermal, Production, Software/Firmware, RTL and more.
The position consists of hands-on testing in lab environment for electrical and optical integration & validation, including problem solving while accompany production and qualification process.

We are seeking a highly motivated architect to join our team of experts and take part in shaping the future of high-performance ML / AI computing. Our next-generation Spectrum-X, InfiniBand and NVLink systems will be at the heart of connecting and powering the world's most advanced compute clusters, from supercomputers used in AI research to high-performance clusters used at almost every industry today. As a system/software architect, you will have the opportunity to work on some of the most innovative technology that is currently driving the world forward.

What youll be doing:

Define the next generations of Spectrum-X, InfiniBand and NVLink SW architecture.

Research of various solutions by defining and running POCs, evaluate SW and HW impact and conveying the solution architecture to the relevant teams. The solutions can span over various layers: from algorithms and high level software to firmware and HW.

Collaborate with multi-functional teams, including other architecture teams, VLSI logic design, system software, firmware, and research teams, to ensure the successful execution of the project.

The complexity of the chip has greatly increased over the years. We are now packing tens of billions of transistors in a chip to meet the growing computing demand in a footprint that is responsible to our environment. The System-On-Chip (SOC) group is looking for a top ASIC Engineer with a curiosity about SOC design automation, RTL integration, chip build and assembly, and padring design and verification. You should have real passion for methodologies and automation solutions that enable SOC creation in the most optimized way.

In this position, you will get the opportunity to build complex networking chips and interact directly with unit-level ASIC, Physical Design, CAD, Package Design, Software, DFT and other teams.


What you'll be doing:

Implement chip level design through collaboration with cross-functional teams (Functional Design, DFT, Design Verification, System Verification, STA, and Physical Design).

Be exposed and work on a variety of functional and structural challenges. Including functional debug, physical design readiness, emulation, resolve design quality issues.

Daily work involves aspects of chip level design, including partitioning, CDC, RDC, trial synthesis, design quality checks.

Taking part in flows development and deployment.

We are seeking a highly skilled and modern software engineer to develop and prototype brand new advancements in distributed training and inference using our Spectrum-X AI fabric. This role offers a rare chance to pioneer AI and networking technology, contributing to ground-breaking projects that will define the landscape of large-scale AI systems. Improve AI app-networking connection by refining communication, crafting congestion control, coding NIC firmware, and expanding switch SDK features for enhanced AI factory efficiency. Your work impacts large AI system development, scaling, and speed.

What youll be doing:

Prototype end-to-end solutions to improve distributed training and disaggregated inference performance.

Analyze and optimize communication flows across application, transport, and network layers.

Develop system software spanning communication libraries, drivers, and firmware integrations.

Collaborate with hardware, firmware, and SDK teams to co-design network features.

Validate and integrate prototypes into our AI infrastructure and products.

We seek for team lead to join our Ethernet Switch SONiC Network OS. As a SONiC design team lead, you will have to work closely with our development and architecture teams responsible for SONiC Network OS and gain a deep understanding of our products and technologies.

What you'll be doing:

Be part of our SONiC R&D team, contribute code to SONiC worldwide community.

Work in a Continuous Deployment environment of fast development/deployment cycles.

Work with experienced teams which are well known in the SONiC community.

Participate in an international team of software engineers working on products for testing our products.

Manage, mentor, and guide a team of SONiC eth switch NOS.

Design and implement SONiC feature under linux environment upstream to SONiC open source project.

Promote a culture of innovation, quality, and accountability. Bring SONiC NOS to shine in customer's view.

We are looking for a Senior Software Engineer to join our team developing the core technologies behind our SmartNIC platform. Your work will directly impact next-generation AI infrastructure, cloud networking, and high-performance data centers used by customers around the world.

What you'll be doing:

Architect, design, and develop next-generation networking acceleration technologies.

Build and enhance core software components within the DOCA SDK.

Work closely with architects, customers, and engineering teams to understand requirements and deliver scalable, high-performance solutions.

Collaborate across the software stack, including applications, virtualization, drivers, Linux kernel, firmware, and hardware teams.

Drive technical decisions and contribute to the design of performant, maintainable software.

We are looking for a Distinguished Engineer to help shape the future of AI infrastructure. As part of our advanced development and research efforts, you will drive technical vision and innovation across the AI software stack, spanning GPU computing, RDMA, NVLink, storage, and large-scale distributed systems. You will research next-generation system designs, influence product and platform direction, and help define how massive-scale AI environments are built, optimized, and operated through hardware-software co-design.

What youll be doing:

Research, define, and drive co-design solutions across AI software stacks involving GPU computing, RDMA networking, NVLink interconnects, storage, and large-scale distributed infrastructure.

Lead deep technical investigations and proof-of-concept development in areas related to distributed AI, deep learning systems, high-performance computing, virtualization, memory management, and large-scale systems design.

Work closely with multiple teams across us to advance next-generation AI infrastructure technologies and influence cross-stack co-design decisions.

Analyze end-to-end system bottlenecks and opportunities across compute, networking, memory, and storage layers to improve performance, scalability, and efficiency.

Guide the design of environments that support massive-scale AI training and inference workloads in production.

We are seeking a highly motivated High-Performance System Architect to join our team of experts and help shape the future of high-performance and ML / AI computing. Our next-generation NVL systems will be at the forefront of connecting and powering the world's most advanced compute clusters, which would be used to train the most advanced AI models such as GPT and DeepSeek. As a high-performance system architect, you will have the opportunity to work on some of the most cutting-edge technology and help to drive the innovation of our next generation networks that will be used by top researchers and engineers around the world.

What youll be doing:

Define the NVL system architecture end-to-end, by internal requirements and customers requirements through all product life cycles (post/pre silicon, on deployments).

Research various of solutions to enable the next large-scale-high-performance computing clusters. The position spans over various layers from algorithms, software, firmware, and HW.

Collaborate with cross-functional teams, including other architecture teams, logic design, system software, firmware, and research teams, to ensure the successful execution of the project.

We are looking for a dedicated SoC Clocks Design Automation Engineer to join our Networking Silicon team. In this role, youll focus on developing and supporting clock-related design flows and methodologies for SoC and networking chips, ensuring efficient and high-quality design implementation. Youll also chip in to SoC top-level automation and integration activities, building on existing flow infrastructure to improve efficiency and consistency across projects. Introduction

What you'll be doing:

Develop and maintain design automation and methodologies for SoC and networking clock flows.

Collaborate with design, STA, and project teams to ensure timely and high-quality design closure.

Develop and improve SoC top-level automation scripts and flows built upon existing infrastructure and tools.

Support SoC integration and construction flow activities across multiple projects.

Assist in timing, power, and noise analysis to ensure efficient performance.

We are seeking a Director of Software Architecture to lead and accelerate the evolution of next-generation AI data center and networking technologies. This role is designed for a hands-on, execution-driven leader who pushes boundaries, translates vision into reality, and delivers high-impact solutions at scale. You will operate at the intersection of innovation, architecture, and delivery-shaping the future of AI networking and infrastructure.

What you will be doing:
Drive identification, evaluation, and rapid adoption of emerging technologies, ensuring strong alignment with strategic roadmap and measurable business outcomes.
Lead the design and delivery of advanced networking applications, leveraging data plane programming and modern networking protocols to solve complex, large-scale challenges.
Architect solutions across AI data center environments, integrating GPU-based systems, hardware acceleration, and high-performance networking.
Act as a thought leader and industry influencer-engaging directly with customers, publishing technical content, and representing us at key conferences and forums.
Define and execute a bold architectural vision for our networking in close collaboration with cross-functional software and hardware leaders.

Required System QA Engineer
The Mission
Your role is to ensure the operational stability and resilience of the Applications Ecosystem, encompassing National C2, MSC2, and Edge C2 platforms. You will rigorously test the seams where these distributed systems integrate. You are expected to execute with precision, learn the architecture deeply from the ground up, and evolve into the Domain Expert
for our multi-tiered command and control system. Critically, you will champion a "Shift-Left" quality approach: preventing defects during the design and planning phases rather than merely catching them after development is complete.
Core Responsibilities:
Actively participate in Product Requirements(PRD), High-Level (HLD) reviews to enforce system testability before code is written.
Execute and automate comprehensive test plans across Edge C2 nodes, MSC2 instances, and National C2 cloud environments.
Validate complex data flows and state synchronization across geographically distributed components.
Simulate degraded network conditions, forced disconnects, and VPN tunnel collapses to validate system recovery and data integrity.
Isolate integration breakdowns between Web Applications and backend microservices.
Analyze complex system logs using modern observability tools to provide developers with exact root-cause indicators and precise reproduction steps.
Integrate automated test suites into the CI/CD pipeline to ensure continuous validation.
Maintain clear, artifact-based documentation of test coverage, system behavior, and defect tracking.

Required RF/HW & System Validation Engineer
Scope:
As an RF/HW Validation Engineer, you will bridge the gap between HW/RF validation and complex system-level testing. You will design, develop, and execute automated and manual test plans to verify the performance, reliability, and compliance of our SDR (Software Defined Radio) architectures and multi-layered tactical systems (including integration with other systems).
Key Responsibilities:
System-Level Testing: Execute end-to-end system testing of counter-drone platforms, verifying the integration of RF hardware, firmware, and complex software-defined radio algorithms under real-world scenarios.
Hardware Product Testing: Test and validate various HW products, including antennas, radar systems, jammers, and related peripherals.
Failure Analysis & Troubleshooting: Debug complex RF anomalies, signal integrity issues, and system bugs down to the component/board level, working closely with RF Design, Board Design, and SW teams.
Documentation: Create comprehensive test plans (ATP/DTP), write test reports, and present data-driven analysis to cross-functional R&D teams to impact the next generation of hardware.

We are looking for an experienced system engineer to participate and lead the development of a radio-based drone detection and mitigation system as part of the company products.
Responsibilities:
Lead features and platforms from ideas to releases.
Guide and participate in the research and analysis of both proprietary and standard radio communication
protocols.
Develop and optimize algorithms for scanning, signal separation, antenna selection, etc.
Define requirements and guide other multi-disciplinary teams (SW, Modem algorithms, DSP, and FPGA) through
implementation and debugging.
Analyze and define complex system behaviors, state machines, algorithms, and event-response logic, including
radio link budget considerations.
Perform independent, hands-on debugging and optimization for system problem-solving using tools like
MATLAB, Python, Excel, and other log analysis software.
Gain a deep understanding of the full system to guide and support development, testing and validation teams.