דרושים » חשמל ואלקטרוניקה » Senior Design Engineer

Requirements:
Minimum Qualifications:
Bachelor's degree in Science, Engineering, or related field and 2+ years of ASIC design, verification, validation, integration, or related work experience.
OR
Master's degree in Science, Engineering, or related field and 1+ year of ASIC design, verification, validation, integration, or related work experience.
OR
PhD in Science, Engineering, or related field.

Preferred Minimum Qualifications:
2-7 years of significant logic design engineering experience.
Knowledge in digital design domain, preferably from the field of ASIC design front end activities.
Hands on experience in micro-architecture definition from specification, RTL development and debug.

Preferred Qualifications:
Experience in RTL implementation in image processing domain (pixel processing, filters, convolution).
Experience in scalable design implementation (definition and coding).
Experience in digital design tools for the following flows: simulation, dynamic verification, synthesis, linting, timing analysis and formal verification.
Ability to work in a team.
Ability to understand system wise aspects like interaction of HW with SW and FW.

Requirements:
You're the right fit if you have:
Bachelor's degree in Electrical Engineering.
A minimum of 10 years of experience in FPGA design in a multidisciplinary industry.
Strong understanding of digital design concepts, clock domains, timing closure, and power optimization.
Ability to create clear and concise design documentation, including design specifications, test plans, and implementation details.
Board design experience and good understanding in schematic, PCB layout, signal integrity analysis, and knowledge of industry standards such as DDR,etc.
In-depth knowledge of FPGA architectures from vendors like Xilinx, Intel (formerly Altera) and signal processing algorithms and techniques for implementing functions efficiently on FPGAs.
Knowledge and experience with high-speed serial interfaces (such as: Ethernet, DDR) and protocols like AXI.
Ability to design and integrate FPGA design into larger systems including interfacing with other hardware components and microprocessors and HW-SW interfaces.
Knowledge and experience in tools/mythologies such as Vivado, Quartus, UVM, and implementation, testing and debugging methods.
Mastery of HDLs like Verilog or VHDL for designing and implementing complex FPGA designs and architectures.
Proficient in debugging techniques and tools for identifying and resolving issues in FPGA designs.
Strong communication skills to effectively collaborate with cross-functional teams including hardware engineers, software engineers, and system engineers.

Requirements:
Technical knowledge in any Interface IP such as PCIe, USB, MIPI, HBM or DDR.
Be familiar with the various stages in the Application-Specific Integrated Circuit design process, including Protocols, Specification, Design, Verification, and Integration.
Excellent organization and solid communication skills are required for customers interactions.
Proven track record in meeting tight schedules and handling projects in parallel.
Experience working with DDR Design, including design, verification, silicon bring-up, and hardware debug.

Requirements:
B.Sc. in Electrical Engineering (or equivalent academic degree)
10+ years in VLSI design (less can be accepted in case of a unique candidate).
At least 5 years as Architect.
Ability to make trade-offs between power, performance, and area appropriately to meet the requirements of the product.
Experience with AI - Mandatory.
Advantages:
Experience with High level design languages like System-c an advantage.
Hardware accelerator development.

Requirements:
4+ years of Logic Design experience.
Experience developing and implementing AMS PHY.
Advanced knowledge of standard ASIC verification flows including simulation and testbench development.
Knowledge about industry standards in PHY Design, including RTL writing and verification tools of RTL.
Deep Understanding of all aspects of PHY construction, Integration and Physical Design.
Working knowledge of Extraction and STA methodology and tools.
Excellent knowledge of System Verilog, Verilog.
Good knowledge of C / C++.
Experience with either Perl/Tcl scripts.
Knowledge of industry standard interfaces and experience with multiple frontend simulators/debuggers.
Deep understanding of Design methodology to debug issues at PHY level.
A teammate with excellent interpersonal skills and the desire to pursue diverse challenges.

Requirements:
5+ years of hands-on experience in ASIC design flow
Solid background in design micro-architecture
Experience in ASIC design front end flows, such as Lint, CDC, RDC
Experience in bus-fabrics and low power design is a plus
Self-starter, highly motivated, highly organized, and schedule-driven
Education & Experience
BSc or MSC in Electrical Engineering or Computer Engineering