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SolarEdge is a global leader in Smart Energy Technology. Our own developed application processors, power controller, PMIC stand at the heart of the company innovation. Joining SolarEdge’s ASIC team will give you the unique opportunity to engage in the entire chip definition and development flow, combining digital and analog circuit designs, from system and architecture to ramp to production. At SolarEdge, HW engineers, SW developers, and ASIC engineers work together in close collaboration to bring to life a complete solution for the solar energy market. We are looking for an ASIC Verification engineer with a good grasp of the entire verification process – plan, execution, and sign-off, excellent analytical skills, technical skills, and high motivation to join our team and take part in the success. What you will be doing:
* Create a thorough verification plan out of IP specification and implement it to completeness.
* Build UVM-compliant IP verification environment from scratch.
* Debug to find the root cause of issues.
* Full-chip verification from planning stage to tape-out, including gate-level testing.
* Testing using SystemVerilog and C.
* Work in a diverse environment, collaborating with power engineers, communication experts, and SW developers.

Country:
Israel

City:
Herzliya

Be part of a dynamic and motivated multi-national Physical Design team, taking part in developing a state of the art Satellite SoC through the full life cycle: design to production.
The chips include complex digital and analog modules. Some of the products are part of the next generation radiation hardened satellite modems. You will have access to best-in-class EDA design tools and will be working in leading edge process technologies.
DFT insertion of complex SoC, VLSI devices and Test Chips, integrating custom designs and 3rd party IP (Hard, Soft, IO, CPUs, DSPs, etc).
Full flow of DFT insertion: MBIST , Scan insertion , ATPG.
Working alongside the Logic Design RTL team to develop timing constraints for implementation at block and chip top level.
Insertion of DFT test structures and chip level integration, capture and simulation.
Jointly with management, build your career development and growth opportunities.