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We are looking for best-in-class Physical Design Engineers to join our outstanding Networking Silicon engineering team, developing the industry's best high-speed communication devices, delivering the highest throughput and lowest latency! Come and take a part in designing our groundbreaking and innovating chips, enjoy working in a meaningful, growing and highly professional environment where you make a significant impact in a technology-focused company.

What you'll be doing:

Physical design of blocks according to specifications under challenging constraints targeting for the best power, area, and performance.
Be exposed and work on a variety of challenging designs (including high cell count and HS blocks). Resolving complex timing and congestion problems.
Daily work involves all aspects of physical design chip development (RTL2GDS) - synthesis, power and clock distribution, place and route, timing closure, power and noise analysis, and physical verification.
Taking part inflows development.

we are establishing a strategic R&D center in Israel to drive the development of complex semiconductor chips that solve the critical 'data bottlenecks' enabling the future of AI at scale. As we expand our presence in Israel, we're seeking a highly skilled Chip Top Physical Design Engineer focusing on implementation to join our local engineering powerhouse from the ground up.
If you thrive on solving complex, unnamed challenges in deep-submicron processes, your place is with us.
As a Physical Design Engineer, you will be a key hands-on member of our PD Team in the Israel R&D center. You will execute the physical design of the SoC Top level for chips that drive the worlds largest AI clusters. You will be deeply involved in all PD disciplines of the chip, driving the tape-out (T.O.) GDS to meet strict signoff criteria (Timing, LVS, EMIR, DRC, PV, etc.), ensuring our silicon meets the extreme performance, power, and area (PPA) targets required for AI scale.
Key Responsibilities
Execute SoC Top-level physical design and actively drive full-chip convergence
Perform Top-Level physical implementation, including floor-planning, Place & Route (P&R), Clock Tree Synthesis (CTS), Power/Clock distribution, Power Integrity, and Timing/Physical signoff
Work closely with the Architecture, Design, DFT, and Product teams to achieve optimal Power, Performance, and Area (PPA). This involves participating in feasibility studies for new architectures and optimizing runs to ensure the best Quality of Results (QoR)
Resolve complex signal integrity, thermal, and power challenges inherent in high-speed connectivity silicon
Collaborate closely with the Package team on Bump-map-to-Ballout design, taking all signal integrity aspects into consideration.

we are establishing a strategic R&D center in Israel to drive the development of complex semiconductor chips that solve the critical 'data bottlenecks' enabling the future of AI at scale. As we expand our presence in Israel, We are looking for a Physical Design CAD Engineer with at least 3 years of hands-on experience in digital implementation flows. The ideal candidate is highly technical, curious, and eager to drive innovation by combining strong physical design knowledge with modern automation and GenAI-based methodologies.
This is a unique opportunity to take on meaningful technical ownership in a new site, implementing the parasitic extraction (PEX) methodologies and flows for chips that power the world's largest AI clusters. As a foundational member of the team, you will be responsible for the accuracy and efficiency of our extraction environment, ensuring that our high-speed designs are modeled with the highest precision from RTL to GDSII.
Key Responsibilities
The Engineer will develop, maintain, and improve CAD flows and methodologies for physical design teams, supporting advanced implementation stages from synthesis through place and route, timing closure, power optimization, and signoff readiness.
Key responsibilities include:
Develop and support physical design CAD flows using industry-standard EDA tools
Build automation infrastructure for implementation, analysis, reporting, and debug
Support design teams in areas such as synthesis, floorplanning, placement, CTS, routing, timing, power, and physical verification
Create scripts and utilities to improve productivity, quality of results, and flow robustness
Support and enhance flows based on Synopsys Fusion Compiler
Explore and integrate GenAI solutions to accelerate debug, automate repetitive tasks, improve reporting, and enhance engineering productivity
Analyze tool results, logs, QoR metrics, timing reports, congestion, utilization, power, and design-rule issues.

Our HW team designs innovative end-to-end connectivity solutions for GPU servers. Our products optimize data center performance and deliver industry-leading bandwidth and scalability. Our products are focused on delivering the most optimized power - performance communication solutions for industries like AI, ML, Cloud, Media and Entertainment as well as any other industry that can benefit from our Datastream acceleration.



What you'll be doing:

Lead Pioneering Switch System design from concept to mass production.

Collaborate and integrate with all HW project fields: Board Design, Mechanics, Thermal, PCB Layout, Production, Software/Firmware, RTL and more.

Project decision maker - Technical focal point.

The position consists of product specification definitions, electrical schematics, component selection, layout guidance, hands-on testing in a lab environment, accompanying production and qualification processes.

We are looking for an experienced Firmware Engineer to join the NIC Firmware team at the Yokneam site. The Firmware team develops cutting edge networking features for cloud, HPC and storage. We drive the data growth of the worlds biggest companies. With talented engineers around the globe, the work environment is dynamic, meaningful, and fast-paced.

What you will be doing:

Work closely with the architecture and different software design teams.

Implement new features in the core of our NIC firmware in pre and post silicon environment.

Develop verification tests for advanced features in a highly complex and sophisticated Firmware testing environment.

Gain a deep understanding of system debug, networking technology and stacks, as well as the HW/FW/SW relationship.

You will learn how a big software project is operated, maintained, qualified and released, and how Hardware and Firmware are developed.

At our company, were building an AI Code Review platform that helps developers move fast, ship with confidence, and elevate code quality across the SDLC through deep, scalable codebase understanding.
We are looking for a motivated and experienced Backend Engineer with 7+ years of hands-on experience to join one of our teams. As a Backend Engineer at our company, you will take ownership of features across the entire development lifecycle - from initial concept and design to deployment and maintenance in an enterprise-grade production environment. This role involves close collaboration with the product team to turn ideas into high-quality, functional software.
Responsibilities:
Develop and lead the end-to-end implementation of new features and product offerings
Design, build, and maintain efficient, reusable, and reliable code across the full stack
Collaborate with product managers and engineers
Participate in all phases of the development lifecycle, including analysis, design, coding, testing, and deployment
Ensure application performance, quality, and responsiveness.

Our HW team in Israel is looking for an experienced System Engineer to join the Hardware Switch Group. The team leads the development of networking infrastructure for our next-generation data centers focusing on accelerated performance while enabling optimized end to end GPU connectivity.

What you'll be doing:
CPO (Co Package Optic) Switch System architecture and design from concept to mass production.
Define the HW requirement, HW arch, board partition and lead electro-optic-mech concept. In addition - design/review HW aspects such as schematics, component selection, layout, opto-mechanics, DFM/T.
Collaborate and integrate with all HW project fields: Board Design, Mechanics, Thermal, Production, Software/Firmware, RTL and more.
The position consists of hands-on testing in lab environment for electrical and optical integration & validation, including problem solving while accompany production and qualification process.

We are looking for an experienced Hardware Engineer (Part-Time - 50% Position) to lead the full hardware development lifecycle, from requirements definition and architecture design to board development, validation, and production support. This is a hands-on role involving close collaboration with Firmware and Software teams, manufacturers, and subcontractors.

We are looking for a talented and experienced engineer to take part in the verification efforts for the companys core product. This position involves building a complex verification environment from scratch, and defining and executing a test plan. In this role, you will be leading verification from A to Z and will have a critical impact on the company.





Responsibilities
Review specifications and develop attributes, tests, and coverage plans
Define methodology and test benches
Work closely with the verification team to ensure the quality of the product
Build and maintain a smart and scalable verification environment that ties into various systems
Work with the software, design, and micro-architecture teams to understand the functional and performance goals of the products design

We are hiring for a Principal/ Senior Backend Engineer to join our fast-paced KSPM (Kubernetes Security Posture Management) team in Cortex Cloud, located in our TLV office. Cortex Cloud is our company's next-generation cloud security solution.
In this role, you'll be key in developing and scaling the core parts of our KSPM solution. Our team's goal is to help Cortex Cloud customers understand and fix security issues in their Kubernetes workloads across all major cloud providers.
The ideal candidates are software engineers with a "can-do" attitude and a passion for solving real customer problems. You should be a person who wishes and is able to work closely with the team and our partners across Cortex Cloud to make decisions and drive features end-to-end.
For us, caring about people is not a slogan; we are looking for individual contributors who enjoy and want to work with great people and collaborate on delivering business value across PANWs vast customer portfolio.
Your Impact
End-to-end backend development of features and core components across the software development life cycle (design, develop, test, deploy, maintain)
As a principal software engineer, independently drive and collaborate with others to deliver high impact features in the KSPM domain
Work with customers and provide solutions to their day-to-day work and challenges
Contribute to team-wide efforts - code reviews, design reviews, technical and architectural decisions.

Our team is responsible for managing the primary entrance gates of customer data to the platform, integrating keen customer understanding with the latest engineering solutions to facilitate high-throughput, minimal-latency, and high-scale data ingestion. We are required to be dynamic and fast, consistently adapting and catching up with the latest technologies employed by our customers to ensure they keep getting the best security coverage for their operational environments and third-party services. We are seeking a Principal/Senior Software Engineer to join a dynamic group that operates with the independence and innovative spirit of a startup, yet benefits from the robust support of a thriving corporation. In this role, you will be instrumental in designing and building high-throughput infrastructure capable of supporting billions of events per second. Your work will involve processing and ensuring the accessibility and visibility of these events to users at peak scales, all while engaging with a diverse range of industry technologies and services.
Key Responsibilities
Responsible for the complete software development lifecycle including requirement analysis, design, development, deployment, and support.
Drive ideas and initiatives, making innovation a reality, and lead your colleagues from ideation through implementation.

We are looking for best-in-class Physical Design Engineers to join our outstanding Networking Silicon engineering team, developing the industry's best high-speed communication devices, delivering the highest throughput and lowest latency! Come and take a part in designing our groundbreaking and innovating chips, enjoy working in a meaningful, growing and highly professional environment where you make a significant impact in a technology-focused company.

What you'll be doing:
Physical design of blocks according to specifications under challenging constraints targeting for the best power, area, and performance.
Be exposed and work on a variety of challenging designs (including high cell count and HS blocks). Resolving complex timing and congestion problems.
Daily work involves all aspects of physical design chip development (RTL2GDS) - synthesis, power and clock distribution, place and route, timing closure, power and noise analysis, and physical verification.
Taking part inflows development.

We are seeking an experienced and talented backend principal software engineer to work with Java in a Spring Boot framework and a microservices architecture. You will face challenges in algorithmics, architecture, and scalability, requiring you to master new technologies and become productive in a short time. You will work with cutting-edge technologies bound to become the next standards in the security industry.
Your Impact
Take part in the development of a large and complex cloud security solution for large organizations.
Master cloud security to develop the most advanced cloud security solution in the market.
Write clean, testable, readable, scalable and maintainable Java code that scales and performs well for thousands of customers.
Develop using the most advanced Java technologies to date.
Design your features in an advanced architecture model built to meet the scalability requirements by our large customers.