לוח משרות דרושים הייטק חומרה משרה מלאה

As a Design Verification Engineer, you will be responsible for ensuring "bug-free first silicon" for complex IP and SoC designs. You will drive all phases of pre-silicon verification, from defining methodologies and test plans to RTL freeze and tape-out sign-off. These roles are highly collaborative, requiring close interaction with architecture, design, and software teams across global sites.
Responsibilities
Architect and develop scalable, portable verification environments, including UVM-based testbenches, protocol monitors, agents, and checkers.
Define detailed test and coverage plans based on micro-architecture specifications and extract features for DV attributes.
Create and simulate test scenarios, perform advanced debugging, and conduct end-to-end simulations of data/control paths.
Drive regression and coverage analysis (metric-driven verification) to ensure the highest quality, productivity, and time-to-market.
Partner with architects and designers from the early stages of feature definition to influence IP/SoC specifications.
Apply formal verification, hardware acceleration, and power/performance (NLP) analysis where applicable.

We are seeking a skilled Digital Hardware & FPGA Engineer to join a team developing advanced avionics systems.
Role Overview:
Lead development of FPGA components in Embedded systems and advanced hardware infrastructures.
Define architecture, implement logic design, and perform simulation and testing in processor-based environments.
Work with high-speed memory and advanced communication interfaces.

we are looking for a Hardware Lead Engineer.
As HW Lead Engineer, in the Nitro team, you will be responsible for defining Annapurna Labs Smart Network Interface Card (NIC) design, leading development and validation cycles, and bringing the product to healthy mass production.
Youll provide leadership in new technologies, bringing them to large-scale deployment, in a continuous effort to deliver a world-class customer experience. We offer a fast-paced, intellectually challenging position, where youll work with technical experts, senior leaders, covering multiple technologies. We are changing the industry, and looking for individuals who are ready for this challenge and want to reach beyond what is possible today.
Key job responsibilities:
- Define the architecture and design specifications of next generation K2 Nitro Cards.
- Own full product life cycle, engage with design partners and manufacturing sites to enable high-yield mass production.
- Lead the analysis and debugging of complex design, manufacturing, and integration challenges.
- Continuously design for process optimization to improve product quality, simplify workflows, and accelerate the Nitro card development lifecycle.

We are looking for an experienced and talented Technical Project Manager with high technical capabilities to join the team.
What you'll do:
Lead the HW development stream of Innovizs products.
Act as a technical project manager and work in a matrix style with all RnD professional disciplines.
Work with multiple teams and disciplines in the RnD and Operations departments and responsible for being the connecting link between the different groups, Opto-mechanics, HW, System architecture, SW, and more.
You will have an end-to-end project management responsibility for the HW deliveries during the project.
As part of the HW deliveries, the technical project manager is responsible for the full design cycle of the HW, from the product and system requirements closure, HW design of the full system (optomechanical and electrical) and releasing all parts to production to full HW integration and bring up. HW deliveries are followed by a full validation phase including HW failure analysis and all according to customers' schedules and delivery plans.
Be responsible for following the design for manufacturing (DFM) practices and working tightly with NPI and production teams.
Be the point of contact (POC) in front of the customer on all HW-related topics, managing and monitoring the day-to-day activities according to the delivery and project plan and according to the companys targets.

The Documentation Team is seeking a Senior Technical Writer to own the end-to-end documentation strategy across multiple platform domains. You will act as a strategic partner to Product and R&D, translating complex engineering concepts into intuitive user guides and high-impact microcopy. Operating in a high-velocity Agile environment with weekly releases, you will drive content excellence while leveraging AI-driven workflows to scale our global documentation footprint.

Responsibilities
Direct the documentation lifecycle for complex platform features, adapters, and weekly release notes across three distinct product squads.
Collaborate with Product Managers and R&D to translate high-velocity technical updates into clear, actionable documentation for enterprise users.
Design and edit intuitive UI copy to guide users through complex cybersecurity workflows and platform interfaces.
Manage high-volume content switching between Platform, Cyber-Physical Assets, and Asset Management domains with timely delivery.

Mechatronics & Components Engineer We are seeking a Mechatronics & Components Engineer to support the development of advanced products through selection, evaluation, and integration of mechanical and electromechanical components.

We are seeking a visionary and results-oriented Hardware Group Director to lead our hardware department.
In this role, you will be responsible for the end-to-end hardware development life cycle, from initial architecture and high-level design to mass production and field support. You will lead a multidisciplinary team of engineers, including mechanical, electronics, motion, and hardware experts, driving innovation while ensuring high-quality execution, on-time delivery, and alignment with company business goals.
Responsibilities
What will you be doing:
Technical Leadership & Strategy:
Define and drive the hardware technology roadmap and architecture for next-generation products.
Lead critical design reviews to ensure engineering excellence and minimize design iterations.
Identify and evaluate emerging technologies and vendors to maintain a competitive edge.
Oversee DFx (Manufacturing, Testing, serviceability) to ensure seamless transition from R&D to production.
Team Leadership & People Management:
Build, lead, and mentor a high-performing multidisciplinary team across electronics, motion, and mechanical engineering.
Foster a culture of innovation, collaboration, and continuous professional growth.
Drive resource planning, project allocation, and performance management processes.
Lead recruitment efforts to attract and retain top-tier engineering talent.
Project Execution & Operations:
Own the end-to-end hardware project lifecycle, ensuring on-time delivery and alignment with budget and quality targets.
Manage relationships with key suppliers and global manufacturing partners.
Oversee departmental budgets, lab infrastructure, equipment procurement, and EDA tool strategy.
Ensure compliance with global regulatory and quality standards.
Cross-Functional Collaboration:
Lead a matrixed hardware group supporting multiple product lines and engineering domains.
Serve as the primary technical interface to executive leadership, providing clear visibility into progress, risks, and mitigation plans.

We are looking for a seeking an HW Expert to lead feasibility, testing and verification the HW system for the next-generation products. You will be actively supporting new product development throughout the R&D life cycle.
Our goal to lead HW multidisciplinary system implementation. We support and work closely with electrical, optical and mechanical R&D teams throughout development next-generation system.
Responsibilities
What you will be doing:
End-to-end ownership of HW feasibility, integration and qualification activities
Active involvement in new products development throughout R&D process life cycle
Preparation of test plans and reports
Lead new products troubleshooting activities during R&D qualifications, first production tool builds and customer beta evaluations
Technical supervision of suppliers, sub-contractors and external labs
Lead jigs development for R&D, production and service.

As a Wireless Design Verification Engineer, you will be part of a team that is responsible for pre-silicon RTL verification of communication subsystems, SoC sub-systems and chip-level functionality. The activity may focus on block level, sub-system level or chip level, including end-to-end simulations of the entire data/control path. You will interact with DV methodologists, designers and communication systems engineers to develop reusable testbench and verification environment deploying the latest methodology with metric driven verification.
Description
- Own critical block and sub-system verification of wireless SoC projects
- Architect and develop testbenches and environments, by using state-of-the-art verification methodologies
- Define verification plan, create, simulate and debug test scenarios
- Drive regression and coverage analysis to ensure high quality DV
- Collaborate with design and systems engineering teams to review requirements, specifications and architecture, extract features and define DV attribute

As a Senior/Staff Design Verification Engineer, you will be a key architect of quality in our Israel R&D center. You won't just run tests-you will design comprehensive verification strategies for high-performance digital blocks, IPs, subsystems, and full-chip integration. You will work at the cutting edge of AI infrastructure connectivity where "good enough" isn't an option, owning end-to-end verification plans for our most challenging designs. If you thrive on solving complex verification challenges and want to ensure the quality of chips powering the world's largest AI clusters, this is your opportunity.

Key Responsibilities

Verification Environment Architecture & Development

Design and develop comprehensive ASIC verification environments across all levels-from unit-level and subsystems to full-chip integration
Build sophisticated SystemVerilog/UVM-based testbenches including protocol/traffic generators, monitors, checkers, and functional coverage models
Own end-to-end verification plans for highly complex digital blocks, defining the "how" and "what" to ensure 100% functional coverage
Quality Assurance & Debug Excellence

Drive the debug process and leverage advanced methodologies to find critical bugs before silicon
Develop and execute comprehensive test plans to verify functionality, performance, and corner cases
Ensure verification closure through rigorous coverage analysis and assertion-based verification
Cross-Functional Collaboration & Technical Leadership

Partner with design and system architects to solve intricate hardware verification challenges
Work alongside world-class teams where knowledge sharing and technical excellence are the standard
Contribute to verification methodology improvements and automation initiatives

we're seeking a highly skilled Chip Top Physical Design Engineer focusing on implementation to join our local engineering powerhouse from the ground up.
If you thrive on solving complex, unnamed challenges in deep-submicron processes, your place is with us.

As a Physical Design Engineer, you will be a key hands-on member of our PD Team in the Israel R&D center. You will execute the physical design of the SoC Top level for chips that drive the worlds largest AI clusters. You will be deeply involved in all PD disciplines of the chip, driving the tape-out (T.O.) GDS to meet strict signoff criteria (Timing, LVS, EMIR, DRC, PV, etc.), ensuring our silicon meets the extreme performance, power, and area (PPA) targets required for AI scale.

Key Responsibilities


Execute SoC Top-level physical design and actively drive full-chip convergence
Perform Top-Level physical implementation, including floor-planning, Place & Route (P&R), Clock Tree Synthesis (CTS), Power/Clock distribution, Power Integrity, and Timing/Physical signoff
Work closely with the Architecture, Design, DFT, and Product teams to achieve optimal Power, Performance, and Area (PPA). This involves participating in feasibility studies for new architectures and optimizing runs to ensure the best Quality of Results (QoR)
Resolve complex signal integrity, thermal, and power challenges inherent in high-speed connectivity silicon
Collaborate closely with the Package team on Bump-map-to-Ballout design, taking all signal integrity aspects into consideration

we're seeking a highly skilled Physical Design CAD Engineer specializing in CAD Automation and Signoff to join our local engineering powerhouse from the ground up.

This is a unique opportunity to take on meaningful technical ownership in a new site, implementing the backend execution environment and methodologies for chips that power the world's largest AI clusters. As a foundational member of the team, you will be responsible for the physical implementation environment. Your primary mission is to develop, optimize, and support automated flows from RTL to manufacturable GDSII tape-out, ensuring a methodical and efficient work environment for the entire PD team.


Key Responsibilities


Develop and maintain automated flows for Synthesis, Place & Route (P&R), and Floor-planning to ensure seamless design transitions
Implement and manage robust environments for Static Timing Analysis (STA), Power Analysis, and Physical Verification (DRC/LVS/ERC)
Write and maintain custom plug-ins and scripts (Tcl/Python) to extend vendor tool capabilities, tailoring them to specific process node constraints
Build automated "dashboards" and feedback loops to track and improve Power, Performance, and Area (PPA) metrics across design iterations
Own the design database structure and version control to ensure team alignment and data integrity
Collaborate directly with EDA vendors (Synopsys, Cadence, Siemens/Mentor) to troubleshoot flow issues and analyze tool results
Provide technical support to the broader PD team, helping them optimize individual blocks for power, performance, and timing