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נאספה מאתר אינטרנט
19/05/2024
Location: Bnei Dror
Job Type: Full Time
We are looking for a Experienced RTL Design Team Leader.
Ready for your next challenge?!
Join our family, enjoy young dynamic environment!
Work on cutting edge projects in the most attractive industry segments (automotive, perceptual computing, medical, communication, etc.)
Requirements:
BSc. in Electrical Engineering (from known university)
Minimum 8 years of experience Must!
Logic design project leader or chip architect
Hands on RTL design with Verilog or System Verilog
Micro architecture definition in CPU/DSP environment
Knowledge in verification (System Verilog, System-C etc.)
Knowledge and experience in the following is advantage:
RTL for FPGA and emulation
AC spec definition
SDC timing constraints write from spec
RT C, C++ ,assembly
Experience with SOC design in DDR, USB, MIPI, ARM subsystem, AMBA, AXI, AHB, DSP, and ARC
Hands on spyglass, synthesis, STA, DFT
Experience with technical customers support or interface
This position is open to all candidates.
 
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נאספה מאתר אינטרנט
08/05/2024
Location: Tel Aviv-Yafo
Job Type: Full Time
We are looking to hire a motivated and skilled core architect to join our system architecture group in Tel Aviv and take part in ramping up our deep learning HW & SW from the ground up. As a team member, you will be responsible for the architecture requirements and definitions of our deep learning processor, as part of our SoCs. You will work closely with the product, algorithms, HW and SW compiler teams to plan and execute the next chip products.
If youre a talented and motivated system architect who is excited about difficult architecture & system challenges, we want to meet you!
Responsibilities:
Define our deep learning processor architecture and SW stack enhancements for different markets and use cases incorporating our products.
Analyze AI pipelines derived by customer and product requirements for current and future products.
Evaluate our products power and performance by developing accurate architectural models and exploring HW & SW architectural changes to enhance product KPIs.
Requirements:
B.Sc./M.Sc. Electrical Engineering or Computer Engineering or related field from a leading university.
3+ years of experience as a system / SW / chip architect or architecture model engineer
5+ years of experience as one of the following:
Logic designer
Verification/system validation engineer
FW / compiler engineer
Advantages
Proficiency in Python or C++
Experience with Deep Neural Networks or other ML methods.
Experience with Deep Learning ASIC architecture.
Experience with graph and low-level compilers.
Experience with HW/SW co-design & partitioning.
Experience with functional safety and automotive qualifications.
This position is open to all candidates.
 
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נאספה מאתר אינטרנט
08/05/2024
Location: Tel Aviv-Yafo
Job Type: Full Time
We are looking to hire a motivated and skilled AI performance system architect to join our system architecture group in Tel Aviv and take part in ramping up our deep learning HW & SW from the ground up.
As a team member, you will be responsible for the performance modeling of our deep learning processor, as part of our SoCs. You will define methods and technologies to model performance at different accuracy levels by supporting architectural explorations and decision-making. If youre a talented and motivated system architect who is excited about difficult architecture & system challenges, we want to meet you!
Responsibilities:
Evaluate our products power and performance by developing accurate architectural models and exploring HW & SW architectural changes to enhance product KPIs.
Analyze AI pipelines derived by customer and product requirements for current and future products.
Define our deep learning processor architecture and SW stack enhancements for different markets and use cases incorporating our products.
Requirements:
B.Sc./M.Sc. Electrical Engineering or Computer Engineering or related field from a leading university.
3+ years of experience as a system / SW / chip architect or architecture model engineer
5+ years of experience as one of the following:
Logic designer
Verification/system validation engineer
FW / compiler engineer
Advantages
Proficiency in Python or C++
Experience with Deep Neural Networks or other ML methods.
Experience with Deep Learning ASIC architecture.
Experience with graph and low-level compilers.
Experience with HW/SW co-design & partitioning.
Experience with functional safety and automotive qualifications.
This position is open to all candidates.
 
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נאספה מאתר אינטרנט
23/05/2024
Location: Tel Aviv-Yafo
Job Type: Full Time
An exciting semiconductor startup is seeking an outstanding lead architect to join the architecture and system engineering team and create and define a SoC and system architecture for a new type of SoC processing big data. The architect will be responsible for the hardware specifications and flow specifications of complicated modules in the chip and in the full system solution. The architect will work closely with the chip design, firmware and software teams.
This is a rare opportunity to influence future processor architectures.

Job Description
Definition and specification of subsystems in the SoC which includes multi-core massively parallel processor, accelerators, network on chip and networking blocks.
Breaking down the sub-system architecture into microarchitectural blocks, firmware, and SW components.
Understanding the system in which the SoC is integrated to and designing the SoC to perfectly fit into the datacentre system.
Requirements:
BSc or higher degree in Electrical Engineering, Computer Science or Computer Engineering.Graduated with honors.
6+ years of experience as a system architect for large, high-end ASIC SoCs.
Experience with multidisciplinary HW/SW systems.
Team player with good communication skills.
Experience in defining requirements and architectures for advanced high-end systems.
Advantage: Deep understanding of datacenter systems.
Advantage: Background in networks and protocols (e.g. Ethernet, IP, DDr4/5).
This position is open to all candidates.
 
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נאספה מאתר אינטרנט
16/05/2024
Location: Hod Hasharon and Haifa
Job Type: Full Time
Required Senior Memory Subsystem Architect
JOB DESCRIPTION
Our goal is to design cutting-edge CPUs for smartphones, servers, and desktops, and we need the very best talent to help us achieve it!
The CPU Architect will take charge of defining a processor on chip inter-connect and coherent fabric that meets the requirement of high performance, high bandwidth, and scalable processing architecture. This architect will utilize his processor experience to deliver a world-class processor ASIC with many advanced features for Huawei products.
Requirements:
REQIRED
BSC, MS or PHD in Electrical Engineering, Computer Engineering, or Computer Science.
Solid understanding of general purpose CPU micro-architecture, including load store unit, caches, cache coherence, memory hierarchy, multi-processor, multi-thread processor systems, memory technologies and memory controllers.
Ability to make trade-offs between power, performance and area to meet the requirements of the product.
Hand-on experience with high power-efficient CPU on chip interconnect, coherent fabric, memory controllers.
At least 8 years experience in architecture in one of the leading CPU companies
Experience modeling microprocessors using higher-level languages, like C/C++.
DESIRED
Co-operate and communicate well with the architecture and design teams.
Interact with the Product System architects, software teams and ASIC chip teams to define the overall architecture of the Processor ASIC including memory hierarchy.
Travel to Beijing and ShenZhen sites may be required.
Good presentation and internal customer interaction skills.
This position is open to all candidates.
 
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נאספה מאתר אינטרנט
20/05/2024
Location: Tel Aviv-Yafo
Job Type: Full Time
Required ASIC Verification Engineer
Verification Group in a growing group responsible for pre-silicon ASIC Verification of complex chips implementing an advanced modem technology.
As part of the role, you will architect, develop & own blocks / sub-subsystem / system-level verification benches. You will be a major contributor to advanced SV UVM methodologies and to infrastructure development. You will be part of an advanced development flow, using state-of-the-art development & Verification tools and will work closely with the chip architects and RTL / VLSI design teams.
RESPONSIBILITIES
The Verification Engineer will be responsible for different HW blocks at module-level and sub-system level and is expected to:
Have an expert-level understanding of assigned HW blocks as well as a good understanding of the block in the context of whole system.
Communicate with architect, designer, algorithm and other verification engineers to lead complex verification tasks, both on module-level and sub-system testing.
Design complete verification environments.
Implement design in full UVM environment.
Perform full block regressions and collection of functional coverage.
Requirements:
Engineering degree with 3+ years of hands-on experience in ASIC verification using UVM System Verilog
Experience in unit-level as well as subsystem/full-chip verification.
Experience working on complex ASIC or SOC designs
Good knowledge of C/C++ is a plus
System-Level understanding
Experience with SOCs in the communications field advantage
This position is open to all candidates.
 
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