Required Senior FPGA engineer.
Responsible for the architecture, development, test and integration of complex FPGAs for high-performance inspection systems.
Understand the existing FPGA architecture and interactions between the various modules comprising the system.
Conceive, experiment and present modular architectural approaches for FPGA applications with high emphasis on testability.
Work closely with software, hardware, system teams, providing documentation, debug support, analytical and technical expertise
Develop RTL code for additional functionality and capabilities. Perform logic synthesis, timing analysis and timing closure.
Develop test bench and simulation tools to verify correct logical functionality.
Requirements:
BS/MS in Electrical Engineering, Computer Science or related area
Over 5 years of experience designing FPGA in VHDL or Verilog, VHDL preferred.
Practical knowledge of RTL design, synthesis, timing closure, simulation and verification test benches.
Hardware bring up and debug experience desired
Expertise in FPGA from Xilinx/Intel (Altera) families, Working with ARM, ZYNQ, DDR3/4, AXI interfaces, High Speed transceivers, PCIe, DSP technology big advantage.
Familiarity with high level programming languages f.e C/C++, System Verilog, High Level Synthesis, Scripts (TCL, Python) big advantage.
Familiarity working with verification engineers using UVM environment big advantage.
Ability to prioritize work assignments and react to a dynamic work environment.
A strong analytical and problem solver abilities with excellent verbal and written communication skills.