לוח משרות דרושים מהנדסים בגבעתיים

We are seeking a talented Technical Program manager to join our software group. In this high-visibility, hands-on role, you will drive forward the development of our software platform by defining the product and technical direction.

Responsibilities:
Collaborate with other team leaders to establish the product and technical vision for the software group.
Lead the planning, development and implementation process of cross-functional teams focused on delivering cutting-edge technology and products.
Oversee project monitoring, reporting, and risk management, from initiation to delivery, addressing intergroup dependencies to ensure timely and successful completion.
Lead process and methodology improvements, proactively addressing issues to achieve business goals.
Help define our next-generation product roadmap and New Product Introduction (NPI) process.

We are looking for a highly experienced product manager expert to join our Product and Architecture team. The Product & Architecture team is responsible for defining, directing, and driving the product strategy for the entire software stack. If you are a Strategic thinker who can translate market needs into actionable product plans while balancing technical feasibility, an excellent communicator, an Influencer and a negotiator-capable of rallying disparate teams around a common vision and resolving conflicts in a fast‑moving startup environment where priorities shift rapidly, you belong with us.

In this high-visibility and influential role, you will take part in building the process of turning customer requests into shippable action items, working with customers and leaders, scientists and researchers and of course developers and engineers in complex, highly technical domains.

Responsibilities:
Strategic product ownership - research market/HPC needs, set roadmap, and define positioning for the accelerator stack.
Feature prioritization & backlog grooming - write clear user stories, enforce acceptance criteria, and balance short‑term delivery with long‑term performance goals.
Cross‑functional leadership - assist managers in leading sprint planning, reviews and retrospectives; coordinate software, firmware, hardware, and customer‑success teams.
Customer advocacy & feedback loop - capture interview insights, translate pain points into technical requirements, and track feature‑adoption metrics.
Performance KPI management - assist leadership in defining throughput/latency/energy targets, oversee benchmark suites (FFT, BLAS, MPI), and report quarterly results against industry leaders.
Continuous product quality improvement - monitor defect rates, regression test coverage and performance regressions; drive actions that reduce technical debt and increase customer confidence.

We are seeking an exceptional Software Team Lead to guide the development of our runtime software stack. This role requires a rare combination of deep technical expertise, hands-on coding ability, and proven leadership experience. You will own the architecture, implementation, and system-level integration of drivers, runtime components, and low-level system software, driving technical excellence and performance across the stack. The ideal candidate thrives under pressure, takes full ownership of outcomes, and sets the bar for quality and innovation in the team.

Responsibilities:
Lead and mentor a team of runtime and embedded software engineers, setting the standard for technical excellence.
Define and drive the architecture, roadmap, and performance expectations for the runtime stack, ensuring scalable, robust, and high-performance solutions.
Oversee cross-team software projects from concept through production, while remaining hands-on in coding, debugging, and system bring-up for critical components.
Establish rigorous standards for testing, CI/CD, and software lifecycle processes, ensuring maintainable and reliable delivery.
Conduct architecture and performance reviews, providing decisive guidance in ambiguous or high-pressure situations.
Collaborate deeply with architecture, compiler, hardware, and platform teams to deliver cohesive, system-level solutions.
Provide technical leadership to resolve conflicts, make tough trade-offs, and uphold engineering excellence.
Recruit, mentor, and retain top-tier engineering talent.

We are looking for an experienced software engineer with a performance oriented view of coding and knowledge in parallel frameworks. Someone who likes to have an end-to-end understanding of HW-SW, and make an impact on the world of accelerated computing to join our SDK group.

Responsibilities:
Play a key role in defining the architecture for the parallel compute framework API, and how it will interact with other common parallel compute frameworks. Integrate parallel frameworks using our SDK.
Ownership and accountability for accelerated solutions of common math libraries using NextSilicon SDK. Owns features end-to-end from requirements to testing.
Play a key role in defining and implementing NextSilicon SDKs and APIs.
Implement accelerated solutions and innovate by understanding our full software stack end-to-end. Identify performance bottlenecks and resolve them.
Work in close collaboration with cross-functional and multidisciplinary teams, including software, hardware, system, research, and apps engineering teams.

We are looking for a talented Code Generation and Optimization Expert. We are looking for a self- , independent engineer to join the team that builds the software infrastructure for accelerating the system in large scale compute environments like data centers and HPC using new CPU core technology. Working on the cutting edge and future ready systems. We work in a development culture that is diverse, flexible and challenging. For persons looking to make an impact and influence the future of computing with personal growth options.

The CodeGen team is developing core components in the automated optimization process that adapts our unique hardware architecture to run any HPC & AI applications, with little to no code modifications required. By using iterative rounds of telemetry and optimization, our compiler is able to intelligently adapt our accelerator into a workload-specific ASIC, at runtime.

We are seeking a talented Code Generation and Optimization Expert to join our bleeding-edge CodeGen team in Israel. In this high-visibility, hands-on role, you will play a pivotal part in building NextSilicons next-generation runtime compiler.

Responsibilities:
Design and maintain the distributed and heterogeneous executable that is generated by our compiler stack.
Using the MLIR framework, transform high level compiler outputs into hardware-specific binary images, memory mappings, execution parameters, resource allocation, region grouping, and cross-domain coordination for distributed systems.
Design and maintain the API layer (libRT.a) connecting compiler-generated code with runtime services, ensuring seamless integration across different execution domains.
Collaborate closely with hardware, architecture, verification and other compiler teams to align software with hardware requirements and behavior.

We are seeking an experienced and highly skilled Software Engineer to join our Runtime Software group. In this role, you will drive the development of the full software stack and architecture behind our revolutionary coprocessor. You will be challenged to deliver high-performance, system-wide solutions, requiring a deep understanding of complex architectural trade-offs and distributed systems.

As a core team member, you will design and implement infrastructure that enables our unique hardware to accelerate diverse applications at scale. You will collaborate across disciplines - working with hardware engineers, compiler developers, and system architects - to optimize execution in a massive, multi-process, and multi-threaded environment.

Responsibilities:
Design and implement next-generation runtime architectures and infrastructures to support evolving product requirements.
Develop environments for the acceleration of massively parallel applications, managing complex process and thread lifecycles.
Define development scopes and roadmaps to ensure the successful delivery of robust software features.
Partner with hardware and compiler teams to bridge the gap between silicon capabilities and software performance.

We are seeking a highly skilled and experienced Research Engineer to join our team. In this role, you will collaborate on developing innovative solutions from concept to implementation and help drive the next major revolution in the computing landscape.

Responsibilities:
Conduct cutting-edge research and experiments in computing and mathematics.
Develop and optimize mathematical algorithms and computations.
Explore new approaches in graph theory, clustering, and related fields to advance a pioneering general-purpose coprocessor architecture.
Analyze data and apply machine learning techniques to improve performance and insights.
Contribute to technical blogs, whitepapers, and scientific publications.
Collaborate with cross-functional teams to translate research into practical solutions.

We are seeking an exceptional Director of AI Software to lead the full AI software stack that powers our next-generation accelerator platform. This executive-level role owns the strategy, architecture, and execution of all AI software components- including frameworks, compilers, runtime, kernels, developer tools, and end-to-end AI workloads.

You will lead multiple teams responsible for running state-of-the-art models (LLaMA, DeepSeek, diffusion, MoE and future generations of AI), building high-performance kernels, integrating industry frameworks, and delivering a developer-friendly stack to customers, which showcases and materializes the full potential of our hardware.

Responsibilities:
Own the vision, roadmap, and execution of the full AI software stack (frameworks, compilers, runtime, kernels, tools).
Lead teams responsible for running and optimizing AI workloads
Deliver first-class support for PyTorch, Triton, IREE, CUDA-compatible flows, and emerging AI frameworks.
Oversee development of high-performance kernels (GEMM, attention, memory ops) and compiler optimizations.
Drive HW/SW co-design with silicon, architecture, and runtime teams to maximize performance and efficiency.
Ensure end-to-end product delivery, including SDKs, toolchains, developer experience, and documentation.
Own benchmarking, performance targets, and competitive analysis
Build, mentor, and scale a multi-disciplinary AI software organization.
Support bring-up, validation, and tuning of new hardware accelerator generations (pre-silicon and post-silicon).

The AI software team is building solutions that enable the latest AI models and workflows to run efficiently on our unique hardware architecture-unlocking a new level of performance

We are seeking a talented engineer to work on our AI software stack and specifically the AI graph compiler which optimizes AI models to run on our hardware architecture.

Responsibilities:
Develop our AI graph compiler and related components in the SW stack.
Drive the performance of AI models running on our unique architecture.

We are seeking a highly skilled AI Application Team Lead to build and lead a team responsible for developing, running, and optimizing large-scale AI workloads on our AI hardware platform. This role focuses on benchmarking state-of-the-art models (e.g., LLaMA, DeepSeek), executing MLPerf suites, analyzing system-level performance, and driving cross-stack optimizations across hardware, runtime, and software frameworks.

The ideal candidate combines strong technical depth in AI/ML systems, hands-on experience with LLM workloads, and leadership capability to guide a high-performance engineering team.

Responsibilities:
Lead and mentor a team of AI application and performance engineers.
Run and optimize AI workloads (LLaMA, DeepSeek, etc.) and execute MLPerf benchmarks.
Analyze end-to-end performance and identify HW/SW bottlenecks.
Develop optimization strategies across models, kernels, frameworks, and runtime.
Build profiling, debugging, and validation tools for large-scale AI workloads.
Collaborate with hardware, compiler, and device software teams to improve performance.

We are seeking a top notch software engineer to drive forward the development of the full software stack and architecture behind our revolutionary coprocessor. You will demonstrate creative and critical thinking capabilities and have a genuine passion for tackling complex low-level software issues.

As part of the memory system team, you will work on design and implementation of new and enhanced features of the memory system to support high performance computing and AI applications in the Maverick accelerator runtime environment.

You will work closely with software engineers, hardware engineers, compiler developers and other stakeholders to enable the most efficient execution of applications on a large scale, multi threaded and highly distributed system across multiple disciplines with a deep OS Internals point of view.

Responsibilities:
Work on design and implementation of new and enhanced features of the memory system for the Maverick accelerator
Develop a high performance, low latency distributed unified virtual memory management system
Work on system software support for the next generation Maverick system
Define feature development scope and plan for successful product delivery.
Wide system impact through collaboration with software engineers, hardware engineers, compiler developers and other stakeholders

We are looking for a talented and experienced engineer to take part in the verification efforts for the companys core product. This position involves building a complex verification environment from scratch, and defining and executing a test plan. In this role, you will be leading verification from A to Z and will have a critical impact on the company.

Responsibilities:
Review specifications and develop attributes, tests, and coverage plans
Define methodology and test benches.
Work closely with the verification team to ensure the quality of the product.
Build and maintain a smart and scalable verification environment that ties into various systems.
Work with the software, design, and micro-architecture teams to understand the functional and performance goals of the products design.

We are looking for an experienced STA Lead Engineer to join our growing BE team. We are working on the most challenging and interesting ASIC chips. Come join us and have a big impact on our groundbreaking and innovative designs.
Responsibilities:
Take part in STA activities for blocks, Sub Systems and Full chip, from definitions to TO.
Analyze timing results, verify correctness and provide timing budget for the different partitions.
Own the timing constraints both for STA and P&R flow.
Working closely with architecture, design, PD and DFT teams to make sure timing closure and ensures product success.
Identify risks and bottlenecks, work closely with PD, RTL and DFT teams, ensuring convergence throughout various project stages.
Participating in design methodology, reviews and tool automation work and definition.
As part of this rule you will gain very good understanding of our HPC and AI designs and sub system as well as product targets.

We are looking for a talented and experienced engineer to participate in the physical design of the companys product for leading one of Nextsilison BE projects. This position involves working with external back-end developers as well as carrying out critical tasks in-house, and leading aggressive back-end initiatives to meet challenging targets in terms of area, timing, and layout. In this role, you will be at the center of the companys design efforts and will have a significant influence on product architecture.

Responsibilities:
Generate and analyze critical block- and chip-level static timing constraints
Spec and define full chip floor plan, including pin placement, partitions, and power grid.
Develop and validate high-performance, low-power clock network guidelines.
Perform critical block-level place and route and create designs that meet timing, area, and power constraints.
Review the vendors physical design verification flow at chip and block level and guide other designers on how to fix LVS and DRC violations.
Work with vendors on defining physical design methodologies and assist in flow development for chip integration.