A global company is looking for Senior VLSI Design Verification Engineer.
Requirements:
Minimum 5 years experience as a Design Verification Engineer- Must.
Deep understanding of OOP/SystemVerilog/UVM - Must.
Experience with scripting languages (Python or Perl).
Must Experience debugging from RTL to system level- MustGood communication &.
teamwork skills - Must.
Preferred Qualifications:
Knowledge or experience with external VIPs.
Experience with Specman/e.
Experience with GLS/UPF.
Experience with formal Jasper/FPV.
Education Requirements:
BSc in Computer Science/Electrical Engineering.