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We are looking for a creative, hands on Senior Networking Research Software Architect to lead the shaping of future AI clusters in data centers. In this role, you will play a key role defining the future of our end-to-end solution for accelerated communication for our AI infrastructure. Software Architects represent us in open source projects, academic collaborations, conferences and standard bodies.
What you'll be doing:
Identify and evaluate new technologies, innovations opportunities for accelerating distributed AI workloads over our networking appliance.
Prototype and deploy ideas over top of the art compute clusters.
Lead design of new networking applications using data plane programming to solve complex networking problems in innovative ways.
Outbound work includes customers engagements, academic collaborations, blogs, RFCs and conference lectures/BOFs.
Define strategic vision for our networking in the AI front.

We are looking for a Solution Researcher to join the Smart-NIC/ DPU Solutions Product Team, based in Israel. As part of this position, you will conduct hands-on research using our most advanced networking and AI building blocks. The encouraged outcome is to proof an end-to-end solutions and blueprints value, to be used by our customers and influencing our next generation network products.
What you'll be doing:
Work closely with customers, product and technical teams across us to identify accelerated compute use cases
Build and implement a research program finding network and compute bottle-necks, use our accelerated computing blocks to demonstrate performance boosts
Integrate key product features and build a full end-to-end story/solution
Build and deliver custom-tailored product demonstrations and Proof Of Concepts for solutions that address critical business needs of our customers
Prepare and deliver technical training presentations for advanced solutions
Conducting regular customer meetings for product updates and introductions to new technology solutions.

We are looking for a Software QA Automation Engineer to join our DPU team. This position will be part of the QA team while the main goal is to test the Network virtualization for DPU and ConnectX, which enables our products to meet the industry-leading benchmarks of efficiency and quality. The ideal candidate will engage in testing SW industry-leading features, be able to learn new features and design, and automate tests.
What you'll be doing:
Review arch design and requirements for new features introduced virtualization R&D, software team.
Design, develop, and execute tests for the new features, as part of software GA releases or update releases.
Report bugs found during execution, assist with reproduction and debugs to understand root cause, verify bug fixes provided by the R&D team, and raise if not fixed.
Execute tests, report the progress of testing, and provide summary reports of testing activity.
Write automation code to increase efficiency, flexibility, and scalability in Python.

We are looking for a world-class Software Engineer to join its Software R&D Linux group. The position would be part of a team that implement the software for cutting edge networking abilities. Our networking is a leading supplier of end-to-end Ethernet and InfiniBand intelligent interconnect solutions and services for servers, storage, and hyper-converged infrastructure. Our networking intelligent interconnect solutions increase data center efficiency by providing the highest throughput and lowest latency, delivering data faster to applications and unlocking system performance. Our networking offers a choice of high-performance solutions: network and multicore processors, network adapters, switches, cables, software, and silicon, that accelerate application runtime and maximize business results for a wide range of markets including high-performance computing, enterprise data centers, Web 2.0, cloud, storage, network security, telecom, and financial services.
What youll be doing:
You will design and implement kernel drivers for our state or art network devices as well as user space libraries that allow network offloads.
Collaborate and debug with teams across the globe to provide the best solutions for our customers.

We are looking for Senior QA Software Test Engineer to join our System Ethernet group. This position will be part of the QA team while the main goal is testing of Ethernet Switch/Router of us. The QA team builds and runs all software and hardware tests to ensure that new releases meet our quality and reliability standards for Ethernet switch. You will take part with tests design , test execution, and automation development including functionally, scale , performance, and interoperability system testing. Beside of that youll spend your time embedded deeply into our development teams, working side by side with the developers, helping us to explore, find and fix our bugs before they can reach our customers
What you'll be doing:
Functional Testing various Layer2 and Layer3 features of OUR-Mellanox Spectrum series Ethernet Switch systems running OUR-Cumulus Linux.
Write detailed feature and system test plans, define and design test beds and topologies.
Report issues found during testing into the defect tracking system and validate the fixes and workarounds.
Develop automated test suites for different features of OUR-Cumulus Linux.
Build and maintain automation required to ensure quality via continuous functional regression.
Collaborate with design, test and other internal engineering groups to identify, report and resolve.

Our invention of the GPU in 1999 sparked the growth of the PC gaming market, redefined modern computer graphics, and revolutionized parallel computing. More recently, GPU deep learning ignited modern AI the next era of computing with the GPU acting as the brain of computers, robots, and self-driving cars that can perceive and understand the world. Today, we are increasingly known as the AI computing company. We are looking to grow our company, and grow with the smartest people in the world. We are looking for you!
We are looking for a Senior Linux Kernel Software Engineer to join the Linux networking drivers R&D team. The work environment is versatile, educational, dynamic and challenging as our employees are currently working on innovative, next-generation network interface card at the forefront of technology in terms of performance.
What youll be doing:
Being part of the Linux Netdev kernel group, working on developing the device driver for our NICs.
Integration and optimization of existing products and solutions with our software stack and hardware capabilities.
Crafting and developing components of the network, security, and storage software stacks.
Executing a complete engineering process, including refining requirements, engineering design of data structures/algorithms, implementation, peer review, developer testing, and post-GA support.
Drive complex technical issues to closure that may occur in the cross-team boundary.

Join a newly formed, industry leading team that develops our next generation CPU core. Work closely with Architects and Designers on cutting edge technology in an open and vibrant environment. Work on the Development of the Cycle Accurate Performance Simulation and Software Tools.
What You Will Be Doing:
Develop C++ core infrastructure of cycle accurate simulation.
Develop software tools to complement simulation e.g., database, data analysis tools, power tools, debug tools etc.
Develop architectural and microarchitectural features to model next generation core.
Work with the design and verification teams to validate the model, and to root cause disconnects between model projections and design (RTL)
Become an expert in core architecture and microarchitecture.

We are looking for SW QA Network Engineer to join NetQ software Management team.
What you'll be doing:
Functional testing to Ethernet features switching & Routing
Testing the Netq Software management system
Writing and execute manual/automation tests in L2/L3 protocols with our switches products.
Problem reporting and verification of problem resolution.
Work closely with R&D/Arc teams and community in order to push bug fixes.

We are looking for best-in-class Physical Design Manager to join our outstanding Networking Silicon engineering team, developing the industry's best high-speed communication devices, delivering the highest throughput and lowest latency! Come and take a part in designing our groundbreaking and innovating chips, enjoy working in a meaningful, growing and highly professional environment where you make a significant impact in a technology-focused company.
What you will be doing:
Leading and mentoring part of the Physical Design-Backend team.
Physical design of blocks/top-level according to specifications under challenging constraints targeting for the best power, area, and performance.
Be exposed and work on a variety of challenging designs (including high cell count and HS blocks). Resolving complex timing and congestion problems.
Daily work involves all aspects of physical design chip development (RTL2GDS) - synthesis, power and clock distribution, place and route, timing closure, power and noise analysis, and physical verification.
Taking part inflows development.
Act as Partition/Unit level physical design technical leader and focal point.

We are looking for best-in-class Physical Design Engineers to join our outstanding Networking Silicon engineering team, developing the industry's best high-speed communication devices, delivering the highest throughput and lowest latency! Come and take a part in designing our groundbreaking and innovating chips, enjoy working in a meaningful, growing and highly professional environment where you make a significant impact in a technology-focused company.
What you will be doing:
Physical design of blocks/top-level according to specifications under challenging constraints targeting for the best power, area, and performance.
Be exposed and work on a variety of challenging designs (including high cell count and HS blocks). Resolving complex timing and congestion problems.
Daily work involves all aspects of physical design chip development (RTL2GDS) - synthesis, power and clock distribution, place and route, timing closure, power and noise analysis, and physical verification.
Taking part inflows development.
Act as Partition/Unit level physical design technical leader and focal point.

We are looking for a best-in-class STA Engineer to join our outstanding Networking Silicon engineering team, developing the industry's best high-speed communication devices, delivering the highest throughput and lowest latency! Come and take a part in designing our groundbreaking large scale and innovating chips, enjoy working in a meaningful, growing and highly professional environment where you make a significant impact in a technology-focused company.
What you will be doing:
Be in charge of full chip level STA convergence from early stages to signoff.
Take part in Full Chip floor plan design and Netlist creation with aim to optimize timing convergence and work efficiency.
Define and optimize, together with CAD, STA signoff flows and methodologies.
Digital Partitions' and analog IPs' timing integration, giving feedback and driving convergence.
Work closely with logic design and DFT engineers to define and implement constraints for the various work modes, including optimizing them for runtime and efficiency.

We are hiring a Senior Firmware Engineer to our Chip Design PCIe Firmware team. You will be joining a team whose primary mission is to work on cutting edge technology network adapters and build the core technology of the next generation devices in a wide range of fields - low-level C layer between HW and FWs, C++ verification environment, automation challenges, and Python testing environment.
What youll be doing:
Take a part in the design, development, test, debug, and optimization of many angles of the next-generation network adapters up to package release
Collaborate with chip design, software, and architecture teams to define and craft legacy and new low-level firmware flow
Improve our team methodologies, and automated process
Support chip design and firmware teams.

We are looking for best-in-class Physical Design Engineers to join our outstanding Networking Silicon engineering team, developing the industry's best high-speed communication devices, delivering the highest throughput and lowest latency! Come and take a part in designing our groundbreaking and innovating chips, enjoy working in a meaningful, growing and highly professional environment where you make a significant impact in a technology-focused company.
What you'll be doing:
Physical design of blocks according to specifications under challenging constraints targeting for the best power, area, and performance.
Be exposed and work on a variety of challenging designs (including high cell count and HS blocks). Resolving complex timing and congestion problems.
Daily work involves all aspects of physical design chip development (RTL2GDS) - synthesis, power and clock distribution, place and route, timing closure, power and noise analysis, and physical verification.
Taking part inflows development.

We are looking for an excellent Software Manager to lead the Driver verification team and make a wide impact on the company products and teams worldwide. We are looking for a hands-on team leader who isn't afraid of taking up new technologies, processes, challenges and tools to make constant improvements in the verification coverage and infrastructure. The team will collaborate closely with our driver developers and architects as well to sync, build and develop verification for our networking driver products.
You will be a part of a cutting-edge Python-based SW project using advanced techniques such as random, white box testing, machine learning and more. You will gain unique knowledge of how operating system works, Linux kernel and the way large-scale networks are constructed.
Are you ready for this challenge?
What youll be doing:
Lead a verification team from the planning stage to execution in the most innovative our networking chips.
Create and own team strategy, roadmaps, and schedules.
Provide clear direction and goals to your team and interact with other teams across the company.
Review and identify improvement opportunities in established processes, infrastructure, and practices to ensure the teams are executing in the most efficient and transparent manner.
Collaborate with peer engineering teams, and program/product management to ensure that product requirements, goals and objectives are met or exceeded.
Mentor and guide the professional and technical development of the team members.

We are looking for a Senior CPU Verification Engineer!
As a member of our CPU Logic Design Team, you will be responsible for the verification of a high performance and low power chip. This position offers you the opportunity to have real impact in a dynamic, technology-focused company impacting major product lines. We have crafted a team of extraordinary people stretching around the globe, whose mission is to push the frontiers of what is possible today and define the platform for the future of computing.
What you'll be doing:
As a member of our core CPU team, you'll own and be responsible for the verification of major parts in the CPU.
Day to day tasks include: Defining the right verification strategy and testplans, writing high-quality verification environment, reference models and tests for high-complex design, debug, and own responsibility for verification readiness.
Collaborate with our Logic Design team and Architecture team, to verify the correctness of your unit.