Join a Highly skilled, energetic team developing the next generation high - end Embedded SOCs and Communication SOCs for the networking industry.
As design engineer in the team, you will have close interfaces with design and verification engineers within the team and with groups design, verification and architecture teams.
You will be responsible for defining micro architecture for blocks, implementing the design in RTL, debug failing tests and resolve bugs, optimizing the design for performance, power and area and design sign off passing LINT and meeting timing
Requirements:
Must have:
BSc. / MSc. university degree in EE/CS, graduation with honors.
5+ years of experience in VLSI design.
Deep knowledge in Verilog.
Experience in micro-architecture and design of complex blocks.
Familiar with the verification process of a block (test plan, coverage, etc.).
Excellent communication skills in English (written and verbal).
Not a must, but an advantage:
Knowledge in networking and networking chips.
Experience with multi-clock domain designs.
Script knowledge (TCL, perl, etc.).
Understanding the timing closure process (synthesis/STA).
Understanding DFT.