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פורסם ע"י המעסיק
06/05/2021
חברה חסויה
Location: Ramla
Job Type: Full Time
Who are we GuardKnox is the automotive industry’s first Cybertech Tier supplier empowering OEMs, Tier 1 suppliers, and the aftermarket to deliver the next generation of software-defined and service-oriented vehicles. GuardKnox’s flexible and scalable solutions enable added connectivity, Zonal E/E Architecture, hosted applications, high-speed routing (including network recovery and service discovery functionalities), vehicle personalization, and security. The company’s pioneering approach to automotive innovation is inspired by technology from the aviation industry, providing GuardKnox with the experience needed to develop secure, high-performance computing solutions using a patented Service-Oriented Architecture (SOA). Founded in 2016, GuardKnox is based in Israel, with subsidiary locations in Stuttgart, Germany, and Detroit, Michigan
An integral part of GuardKnox product development is our Hardware Development team. The team is responsible for the core hardware and logic design which powers GuardKnox’s embedded solutions. The Senior FPGA Design Engineer will be responsible for high reliable real-time FPGA logic development as well as hardware design, including design of low-level drivers and conversion from code to logic.

Responsibilities Include:

* High reliably FPGA logic development
* Design of system architecture and data flow on a SOC with processors and FPGA logic
* Design high-performance pipeline architectures
* Integration of soft-core IP controllers
* Transition of functionality from software to FPGA logic
* IP’s selection and integration
* Run basic verification tests (on simulations)
* Work on target integration and testing
* Development in accordance with safety and cybersecurity standards
Requirements:
* Bachelors’ degree in Electrical Engineering, Software Engineering or Computer Science
* 4 years of experience as hands-on with FPGA development
* Experience with VHDL/Verilog (System Verilog – Advantage)
* Hands-on experience with synchronous and high-performance pipeline architecture
* Experience with block-level verifications
* Familiarity with Xilinx/ALTERA/Lattice FPGA architecture
 
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