As a SoC Design for Test (DFT) Engineer, you will be responsible for defining, implementing, and deploying advanced DFT methodologies for digital or mixed-signal chips. You will define silicon test strategies, DFT architecture, and create DFT specifications for next generation SoCs. You'll design, insert, and verify the DFT logic and prepare for post silicon and co-work/debug with test engineers. In addition, you will be responsible for reducing test cost, increasing production quality, and enhancing yield.
Behind everything our users see online is the architecture built by the Technical Infrastructure team to keep it running. From developing and maintaining our data centers to building the next generation of Google platforms, we make Google's product portfolio possible. We're proud to be our engineers' engineers and love voiding warranties by taking things apart so we can rebuild them. We keep our networks up and running, ensuring our users have the best and fastest experience possible.
Responsibilities
Develop DFT strategy and architecture (e.g., hierarchical DFT, Memory Built-In Self Test (MBIST), ATPG).
Complete all Test Design Rule Checks (TDRC) and Design changes to fix TDRC violations to achieve high-test quality.
Insert DFT logic, boundary scan, scan chains, DFT Compression, Logic BIST, TAP controller, Clock Control block, and other DFT IP blocks.
Insert and hook up MBIST logic including test collar around memories, MBIST controllers, eFuse logic, and connect to core and TAP interfaces.
Document DFT architecture, test sequences, and boot-up sequences associated with test pins.
Requirements: Bachelor's degree in Electrical Engineering, a related field, or equivalent practical experience.
3 years of experience with Design For Test (DFT) methodologies, DFT verification, and industry-standard DFT tools.
Experience with ASIC DFT synthesis, simulation, and verification flow.
Experience using Electronic Design Automation (EDA) test tools (e.g., Spyglass, Tessent, etc.).
Preferred qualifications:
Master's degree in Electrical Engineering or a related field.
Experience in IP integration (e.g., memories, test controllers, Test Access Point (TAP), and Memory Built-In Self Test (MBIST)).
Experience in fault modeling.
Experience in SoC cycles, including silicon bringup and silicon debug activities.
Experience working with ATE engineers (e.g., silicon bring-up, patterns generation, debug, validation on automatic test equipment, debug of silicon issues).
This position is open to all candidates.
