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We are looking for a talented and driven VLSI CAD Automation & DevOps Engineer to join our team. This role combines expertise in front-end automation, continuous integration, CAD tooling, and full-stack development to support and enhance our VLSI verification workflows.
What will your job look like:
Flow & CI/CD Automation
Automate RTL lint, CDC/RDC, synthesis checks (front‑end only), and UVM regression flows.
Build and maintain CI/CD pipelines (Jenkins/GitLab CI) for simulation, coverage collection, and sign‑off checks.
Implement pre‑submit checks (lint, CDC) and nightly regressions with dashboards for pass/fail and coverage metrics.
EDA Tooling & CAD Enablement
Manage and integrate front‑end EDA tools (e.g., VCS, Xcelium, Questa, SpyGlass).Develop scripts to parse logs/reports (lint, CDC, coverage, simulation) and generate actionable summaries.
Maintain PDK-independent front‑end tool configurations and flow reproducibility.
Compute & Licensing
Operate and optimize compute farm schedulers (LSF/SLURM/Grid Engine) for simulation and regression jobs.
Monitor and tune license usage for front‑end tools (FlexLM/Lmx), ensuring high availability and efficiency.
Observability & Support
Build dashboards for regression health, coverage trends, and farm/license utilization.
Troubleshoot flow failures, triage environment vs. design issues, and publish runbooks for common problems.

Were looking for a student to join the growing Physical Design Team, responsible for state of the art SoC design from definition to Tape-Out.
What will your job look like?
Hands-on physical design block owner from RTL to GDS.
Floorplan exploration with guidance and collaboration with front-end and architecture teams.
STA: work with FE and floor planner to manage block and top level constraints and 1st level of timing analysis.
Synthesis exploration and final synthesis netlist: Scan insertion @ synthesis, clean checks from Lint, UPF & Spyglass.
Place & Route: from Synthesis netlist to final layout and signoff verification with target to achieve best power performance and area.

We are looking for a skilled Senior Storage Engineer who is passionate about service excellence and eager to join a dynamic team.
Join our HPC Team and be a key player in shaping the exciting infrastructure that underpins our autonomous driving future!
How will your job look like?
Manage and maintain our heterogeneous data center Storage and HPC infrastructure
Collaborate with development teams to fully understand their requirements and design storage architectures that meet those needs
Architect and maintain next-generation distributed storage systems, including object storage, file storage, and more
Tackle complex challenges and demonstrate advanced problem-solving skills in high-availability environments
Operate within complex, mission-critical data centers, working alongside domain experts to ensure optimal performance of Storage and HPC solutions
Perform planning, performance tuning, optimization, hardware/firmware configuration, and device hardening.

Required Senior HW System Architect
We provide modular automotive systems that transform mobility by bringing cutting-edge, safe-by-design self-driving technology and a complete, modular solution with flexible business models to the market.
As a Senior HW System Architect, your role will be to work closely with our OEM partners and realize a successful integration of the ADAS to self-driving technology in these platforms.
This role requires working from our Jerusalem site at least 1 day per week. It also offers the flexibility to work part-time from our other sites, subject to seat availability.
What will your job look like?
Lead end-to-end life cycle of the System architecture - from analyzing OEMs (customers) technical requirements to HW architecture definition, development and verification to ensure integration of our products into the vehicle platform.
Work in close collaboration with various groups including algo, HW design, verification, SW architect, Mechanics, and simulations.
Provide architectural guidance and tradeoff recommendations throughout the whole design process from concept through production.
Responsible for the main components selection and technical evaluation (trade-off between cost/performance etc.)
Provide practical system architecture definition to board designers and SW/algo by managing system external Interconnects and internal interfaces, SoC, MCU, definitions and optimization (based on OEMs requirements and other constraints).

Were looking for a Physical Design Timing Expert to join the growing Technology Methodology & Execution team, that is responsible for developing both Technology Methodologies & Flows for all products and processes and the execution of complex Subsystems/IPs for our next generation Imagining Radar SoC from definition to Tape-Out.
What will your job look like:
Leading Subsystem/IP Timing activities for complex Sub FullChip with several levels of hierarchies.
Timing rollup , analysis & of blocks & sub system levels & timing signoff on Function & Scan models on Sub FC /IP level.
Define timing signoff methodologies, corners, derates margins and improve QoR & convergence.
Involved in the chip design & architecture definition for both functional & DFT domain.
Serve as the technical STA lead while mentoring and guiding team members.

Were looking for a Physical Design STA Technical Expert to join the growing Physical Design Team, responsible for state of the art SoC design from definition to Tape-Out.
What will your job look like:
Leading FC timing activities & methodologies for brand New SoC, from definition to TO.
Writing design constraints (SDC) for FC/IP/Block levels for all modes.
Involved in chip architecture definition for functional & DFT domains.
Working in close collaboration with the front-end & architecture team.
Working with engineers to identify and overcome roadblocks and obstacles.
Defining AC timing from spec to implementation.
Supporting complex clock structures.

Were looking for a Physical Design Expert to join the growing Technology Methodology & Execution team, that is responsible for developing both Technology Methodologies & Flows for all products and processes and the execution of complex Subsystems/IPs for our next generation Imagining Radar SoC from definition to Tape-Out.
What will your job look like:
Hands-on physical design block or IP owner from RTL to GDS with horizontal domain ownership.
Collaboration with front-end and architecture teams to address issues, define design methodologies and improve QoR & convergence.
End to End ownership from Synthesis, DFT insertion, Floor Planning , Place & Route till signoff.
Signoff on all domains- STA, IR/EM, Physical Verification, Logic Equivalent Checking, Low Power Verification.
Exploratio of different methodologies from P&R till signoff to improve PPA & Turnaround time.
Evaluation of new technologies tools & features and to bring innovation with significant RoI.
Technical support and mentoring the engineers in the team.

Were looking for a Physical Design Engineer to join the growing Physical Design Team, responsible for state of the art SoC design from definition to Tape-Out.
What will your job look like:
Hands-on physical design block owner from RTL to GDS.
Floorplan exploration with guidance and collaboration with front-end and architecture teams.
STA: work with FE and floor planner to manage block and top level constraints and 1st level of timing analysis.
Synthesis exploration and final synthesis netlist: Scan insertion @ synthesis, clean checks from Lint, UPF & Spyglass.
Place & Route: from Synthesis netlist to final layout and signoff verification with target to achieve best power performance and area.