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we are seeking a highly motivated Power Integrity Engineer to join our Hardware Engineering team. In this role, you will be responsible for defining, analyzing, simulating, and validating power delivery networks (PDNs) for next-generation networking platforms supporting high-performance ASICs, advanced SerDes interfaces, optical modules, and AI-scale networking systems.
You will work closely with hardware architects, PCB designers, ASIC teams, signal integrity engineers, mechanical engineers, and manufacturing partners to ensure robust power delivery, optimal system performance, and successful product deployment.
Responsibilities
Lead Power Integrity (PI) activities throughout the hardware development lifecycle, from architecture through production.
Define and optimize board-level and package-level Power Delivery Networks (PDNs) for high-current networking ASICs and supporting devices.
Perform pre-layout and post-layout PI simulations using industry-standard tools.
Establish target impedance requirements and validate compliance across all power rails.
Analyze DC voltage drop, AC impedance, transient response, and power distribution performance.
Collaborate with PCB layout engineers to optimize stackups, plane structures, decoupling strategies, and power routing.
Work closely with Signal Integrity engineers to ensure SI/PI co-optimization of high-speed interfaces.
Develop power integrity design guidelines and best practices for next-generation networking products.
Support schematic reviews, layout reviews, and design sign-off activities.
Perform laboratory measurements and correlation using oscilloscopes, VNAs, power analyzers, current probes, and related equipment.
Investigate and resolve PI-related issues during board bring-up, validation, and production.
Collaborate with ASIC, FPGA, memory, optics, and power component vendors to optimize overall system performance.
Drive continuous improvement of PI methodologies, simulation flows, and validation processes.

We are looking for an experienced Senior Signal Integrity Engineer to join our Hardware Engineering team. This role focuses on ensuring optimal signal integrity for high-speed interfaces, including Ethernet, PCIe, DDR5, and other next-generation technologies. As part of the team, you will be responsible for performing signal integrity analysis, developing signal integrity models, and ensuring electrical compliance for high-speed SERDES I/Os.
Responsibilities:
Conduct signal integrity analysis and simulations for high-speed interfaces such as 112Gbps Ethernet, PCIe Gen5, and DDR5 interfaces.
Develop and implement signal integrity guidelines for PCB design, ensuring high-performance and low-loss signal paths.
Analyze and resolve signal integrity issues related to high-speed interfaces, including reflection, crosstalk, and power delivery network (PDN) issues.
Collaborate with PCB layout engineers to optimize design for signal integrity, ensuring compliance with electrical standards and high-speed design best practices.
Perform time-domain and frequency-domain analysis, including loss, jitter, and eye-diagram analysis.
Utilize EDA tools such as Ansys SIWAVE, HFSS, or similar for simulation and validation of signal integrity designs.
Work closely with cross-functional teams to integrate signal integrity considerations into the overall hardware design process.
Develop behavioural models based on measured signal integrity data to inform future design and simulation work.
Conduct pre- and post-layout simulations and measurements for high-speed signal interfaces.

The Power Design team is responsible for driving power efficiency throughout the chip design lifecycle, from early architecture and RTL through physical implementation and final signoff.
The team develops and owns the methodologies, tools, and flows used to estimate, analyze, track, and optimize chip power. We work closely with architecture, RTL, verification, and physical design teams to identify power challenges early, understand their root causes, and drive effective solutions while balancing power, performance, and area (PPA).
Our work includes developing power models and estimation capabilities, analyzing power at different stages of the design flow, identifying optimization opportunities, and driving improvements at both the RTL and physical design levels. The team also explores new automation and AI-based methodologies to make power analysis faster, more accurate, and more actionable.
As the chips power center of expertise, the team provides technical guidance, establishes best practices, tracks power targets, and drives power-related activities across the broader chip design organization.
What You Can Expect

Ramp up on chip power estimation methodologies, tools, and power calculators.

Perform power analysis and identify optimization opportunities throughout the chip design lifecycle.

Explore and implement power optimizations at both the RTL and physical design levels.

Develop automation and improve existing power analysis and estimation flows.

Explore the use of AI tools for power analysis, optimization, and design-flow automation.

Analyze power trends and identify high-impact areas for improvement.

Collaborate with RTL, physical design, architecture, and power teams to drive power-related activities.

Gradually become a power focal point within the chip design team, building expertise and ownership of power methodologies, analysis, and optimization.